Embedded Systems Design
Course Description
Learn general embedded concepts, tools, and techniques using the AMD Vivado™ Design Suite and AMD Vitis™ Unified IDE.
The emphasis is on:
- Designing, expanding, and modifying embedded systems utilizing the features and capabilities of the Zynq™ System on a Chip (SoC), Zynq UltraScale+™ MPSoC, Versal™ adaptive SoC, and MicroBlaze™ soft processor
- Adding and simulating AXI-based peripherals using bus functional model (BFM) simulation
What's New for 2023.2
- All labs have been updated to the latest software versions
Level
Embedded Hardware 3
Course Duration
2 day
Audience
Engineers who are interested in developing embedded systems with the Zynq SoC, Zynq UltraScale+ MPSoC, Versal adaptive SoC, and/or MicroBlaze soft processor core.
Prerequisites
- FPGA design experience
- Completion of the Designing FPGAs Using the Vivado Design Suite 1 course or equivalent knowledge of the Vivado software implementation tools
- Basic understanding of C programming
- Basic understanding of microprocessors
- Some HDL modeling experience
Software Tools
- Vivado Design Suite 2023.2
- Vitis Unified IDE 2023.2
Hardware
- Architectures: Zynq-7000 SoC (Cortex™-A9 processor), Zynq UltraScale+ MPSoC (Cortex-A53 and Cortex-R5 processors), Versal adaptive SoC (Cortex-A72 and Cortex-R5F processors), and MicroBlaze processor
- Demo board: Zynq UltraScale+ MPSoC ZCU104 or Versal adapative SoC VCK190 board*
* Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
- Describe the various tools that encompass a AMD embedded design
- Rapidly architect an embedded system containing various processors using the Vivado IP integrator and Customization Wizard
- Develop software applications utilizing the Vitis unified software platform
- Create and integrate an IP-based processing system component in the Vivado Design Suite
- Design and add a custom AXI interface-based peripheral to the embedded processing system
- Simulate a custom AXI interface-based peripheral using a verification IP (VIP)
- Investigate issues using cross-triggering
Course Outline
Day 1
- Embedded UltraFast Design Methodology – Outlines the different elements that comprise the Embedded Design Methodology. {Lecture, Demo}
- Overview of Embedded Hardware Development – Overview of the embedded hardware development flow. {Lecture, Demo}
- Driving the IP Integrator Tool – Describes how to access and effectively use the IPI tool. {Lecture, Lab}
- Overview of Embedded Software Development – Reviews the process of building a user application.{Lecture}
- Driving the AMD Vitis Unified IDE – Introduces the terminology and features of the Vitis Unified IDE and covers the basic behaviors required to drive the Vitis Unified IDE to generate a C/C++ application. {Lecture, Lab}
- AXI: Introduction – Introduces the AXI protocol. {Lecture}
- AXI: Variations – Describes the differences and similarities among the three primary AXI variations. {Lecture}
- AXI: Transactions – Describes different types of AXI transactions. {Lecture, Lab, Demo}
- Introduction to Interrupts – Introduces the concept of interrupts, basic terminology, and generic implementation. {Lecture}
- Interrupts: Hardware Architecture and Support – Reviews the hardware that is typically available to help implement and manage interrupts. {Lecture}
Day 2
- AXI: Connecting AXI IP – Describes the relationships between different types of AXI interfaces and how they can be connected to form hierarchies. {Lecture, Demo}
- Creating a New AXI IP with the Wizard – Explains how to use the Create and Import Wizard to create and package an AXI IP. {Lecture, Lab}
- AXI: BFM Simulation Using Verification IP – Describes how to perform BFM simulation using the Verification IP. {Lecture, Lab}
- MicroBlaze Processor Architecture Overview – Overview of the MicroBlaze microprocessor architecture. {Lecture, Lab}
- MicroBlaze Processor Block Memory Usage – Highlights how blockRAM can be used with the MicroBlaze processor. {Lecture}
- Zynq-7000 SoC Architecture Overview – Overview of the Zynq-7000 SoC architecture. {Lecture, Demo, Lab}
- Zynq UltraScale+ MPSoC Architecture Overview – Overview of the Zynq UltraScale+ MPSoC architecture.{Lecture, Demo, Lab}
- Debugging Using Cross-Triggering - Investigate causes of hidden problems in both hardware and software. {Lecture, Lab}